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note: this is a summary document. the complete document is available under nda. for more information, please contact your local atmel sales office. features ? supported data rate 0.5k to 20kbit/s manchester (higher data rates in transparent mode) ? programmable rx-if bandwidth 25khz to 360khz (approx. 10% increments) ? frequency ranges 310mhz to 318mhz, 418mhz to 477mhz, and 836mhz to 928mhz ? 315.00mhz/433.92mhz/868.30m hz and 915.00mhz with 24.305mhz crystal freq. ? programmable channel frequency with fractional pll ? 92hz resolution for low band ? 184hz resolution for high band ? fsk deviation 0.375khz to 90khz ? fsk sensitivity (manchester) at 433.92mhz ? ?106dbm at 20kbit/s, f = 20khz, ifbw = 165khz ? ?109dbm at 10kbit/s, f = 10khz, ifbw = 165khz ? ?111dbm at 5kbit/s, f = 5khz, ifbw = 165khz ? ?119dbm at 0.75kbit/s, f = 0.75khz, ifbw = 25khz ? ask sensitivity (manchester) at 433.92mhz ? ?108dbm at 20kbit/s, bw = 360khz ? ?116dbm at 1kbit/s, bw = 360khz ? excellent blocking (ifbw = 165 khz): 64dbc at freq. offset = 1mhz and 50dbc at 225khz ? high image rejection typ. 55db (315mhz/ 433.92mhz); typ. 50db (868.3mhz/915mhz) without calibration ? input 1db comp ression point ? typ. ?35dbm (full sensitivity level) ? typ. ?20dbm (15db reduced sensitivity) ? digital rssi with accuracy of 5db and 0.5db resolution ? low current consumption ? typ. 9.3ma for rx (low band) typ. 580a 3 channel polling ? max. power down current co nsumption of 600na at v s = 3.6v and t = 85c ? programmable clock output derived from crystal frequency ? 24kbyte of rom with atmel firmware ? 512 bytes of eeprom data memory for rece iver configuration an d 768 bytes of sram ? spi interface for rx data access and receiver configuration ? irq signal indicates the ic condition status ? automatic application channel pol ling (3 rke channels, tpms, rs) ? id scanning up to 18 different id s (id lengths of up to 4 bytes) ? supply voltage range 1.9v to 3.6v and 4.5v to 5.5v ? temperature range ?40c to +105c ? excellent esd protection at all pi ns (4kv hbm, 200v mm, 750v fcdm) ? small 5mm 5mm qfn 32 package pin/pitch 0.5mm ? pin compatible ic with rx performance id entical with the atmel ata5830 transceiver ? appropriate for application systems co mpliant with en 300 220 and fcc 15 uhf ask/fsk receiver atmel ata5780 summary preliminary 9207bs?rke?01/11
2 9207bs?rke?01/11 atmel ata5780 [preliminary] 1. general product description 1.1 overview the atmel ? ata5780 is a universal, highly integr ated, low-power uhf ask/fsk single chip rf receiver. this ic contains the rf part, digital baseband and the avr ? microcontroller core. the core is a low-power cmos 8-bit microcon troller with enhanced ri sc architecture. the receiver is designed for ism frequency bands in the 310mhz to 318mhz, 418mhz to 477mhz, and 836mhz to 928mhz ranges respectively while featuring a high degree of integration, which reduces the number of external elements. outstanding rf performance and sophisti- cated baseband signal processing enables robust wireless communication. the receiver is designed using super heterodyne architecture with an integrated low-if double quadrature mixer. this architecture features high image rejection and excellent blocking performance. its flexible, configurable baseband signal processing also allows the receiver to operate in sev- eral scanning, wake-up, and au tomatic self-polling scenarios. during scanning the ic can seek specific message content (ids) and in case of a valid telegram the data is stored in the fifo data buffer. the two fully independent receiving baseband paths enable receiving and pro- cessing of two different incoming signals. the configuration of these signals can differ in modulation, data rate or wake-up scenario. the autonomous scanning of three different appli- cation channels with varying configuration is s upported. the settings of the receiver are stored in a 512-byte eeprom. the device can be configured and accessed via an spi interface. 1.2 application 1.2.1 target applications the receiver is designed for use in the following application areas: ?remote keyless entry system (rke) ? tire pressure monito ring system (tpms) ? remote start system (rs) ? remote control system, e.g. garage door openers ? smart rf appl ications because of its flexibility the rece iver can combine up to three diffe rent application types in the autonomous self-polling setting.
3 9207bs?rke?01/11 atmel ata5780 [preliminary] 1.2.2 typical application circuits figure 1-1. typical 5v application circuits 1.3 main extended featu res of the ata5780 1.3.1 outstanding rf performance the atmel ? ata5780 uhf receiver is highly sensitive. its high image rejection and outstand- ing blocking performance make a robust applicati on against interferer possible in a low cost design. the programmable channel filter bandwidth additionally provides flexibility to address different system requirements. 1.3.2 automatic self-polling and multi-channel capability the autonomous self-po lling supports the automatic scanning of three different applications. in the automotive car access market the remote keyless entry (rke), tire pressure monitor- ing system (tpms), and remote start (rs) applic ation can be supported with a single ic. in addition, multi-channel systems of up to three frequencies can be used. all five different fre- quencies can be scanned in the autonomous polling scheme, three frequencies for rke, a single frequency for tpms, and also a single frequency for rs. completely different and unique configuration of each applic ation type is supported. this is possible due to the flexibility of the digital baseband and two different baseband reception paths. the ic can be operated without having to be initial configured by an external microcontroller. 1.3.3 wake-up scenario and id scanning the baseband signal processing is designed to reduce host controller processing load. for this purpose the receiver has to find the right telegram (message content) first before the host controller is woken up. the criterion for the wake-up can be determined using a pattern and id within the telegram. before the host controller is woken up, the receiver has to find both the correct pattern in the preburst and the valid id. rfin_lb at e s t _io1 te s t _io2 rfin_hb agnd rx_ a ctive led0 npwron6 irq n ss pwron led1 mi s o npwron1 nre s et v s avcc xtal2 xtal1 te s t_en s pdt_rx s pdt_ant npwron2 trpa npwron 3 tmdo npwron5 trpb tmdo_clk n.c. n.c. n.c. n.c. mo s i 3 2 1 2 3 4 5 6 7 8 24 2 3 22 21 20 19 1 8 17 3 1 3 0292 8 27 26 25 91011121 3 14 15 16 s ck clk_out dgnd n ss mi s o mo s i s ck dvcc npwron4 v s = 4.5v to 5.5v microcontroller atmel ata57 8 0
4 9207bs?rke?01/11 atmel ata5780 [preliminary] 1.3.4 two separated reception paths the receiver?s demodulator contains two separate data paths. the parameters for either path can be set differently, e.g. the modulation type or data rate. both paths generally work simulta- neously, but the first valid data from one of the both paths is stored on the buffer, which can be read by using the spi command. 1.3.5 channel statistic in order to accelerate the communication in multi-channeling the atmel ata5780 offers a fea- ture defined as channel statistic. if this feature is activated, the ic will find the best channel having the least interference within the three frequency channels and select the best channel as the first operating frequency during transmission. 1.3.6 application firmware all the functionality described in the datasheet is implemented in 24-kbyte rom firmware. 1.4 pin diagram and confi guration of atmel ata5780 figure 1-2. pin diagram note: the exposed die pad is connected to the internal die rfin_lb rfin_hb agnd rx_active/led0/npwron6 irq n ss pwron/led1 mi s o npwron2/trpa npwron1 nre s et v s avcc xtal2 xtal1 te s t_en s pdt_rx s pdt_ant n.c. n.c. n.c. n.c. mo s i 3 2 1 2 expo s ed die p a d 3 4 5 6 7 8 24 2 3 22 21 20 19 1 8 17 3 1 3 0292 8 27 26 25 9 1011121 3 14 15 16 s ck clk_out dgnd dvcc npwron5/trpb/tmdo-clk npwron4 npwron 3 /tmdo atmel ata57 8 0 te s t_io2 at e s t_io1
5 9207bs?rke?01/11 atmel ata5780 [preliminary] 1.5 compatibility with the atmel uhf transceiver ata5830 this ic is pin compatible to the transceiver ata5830. the ic has the identical rx perfor- mance of the atmel ? ata5830 rx path. the difference is on the digital block. the receiver does not contain a free usable microcontroller and is operated using a rom-only programmed avr ? as state machine without flash or tx part. this receiver is therefore fully compatible with the transceiver and can also be customized via eeprom settings. table 1-1. pin configuration pin no. pin name type function 1 rfin_lb analog lna input for low-band frequency range (< 500mhz) 2 rfin_hb analog lna input for high-band frequency range (> 500mhz) 3 spdt_rx analog rx switch output (damped signal output) 4 spdt_ant analog antenna input for the switch 5 nc not connected 6 nc not connected 7 nc not connected 8 nc not connected 9 test_en test enable, works with avcc voltage 10 xtal1 analog crystal oscillator pin1 (input) 11 xtal2 analog crystal oscillator pin2 (output) 12 avcc analog rf front-end supply regulator output 13 vs analog main supply voltage input 14 nreset digital nreset 15 npwron1 digital npwron1 16 npwron2 / trpa digital npwron2/trpa 17 npwron3 / tmdo digital npwron3/tmdo 18 npwron4 digital npwron4 19 npwron5 / trpb / tmdo_clk digital npwron5/trpb/tmdo_clk 20 dvcc digital supply voltage 21 dgnd digital ground 22 clk_out digital clk_out 23 sck digital sck 24 mosi digital mosi (master out/spi slave in) 25 miso digital miso (mast er int/spi slave out) 26 pwron / led1 digital pwron/led1 (strong high-side driver) 27 nss digital nss 28 irq digital irq (software-controlled external microcontroller interrupt flag) 29 npwron6 / rx_active / led0 digital npwron6/rx_active (strong high-side driver)/led0 (strong low-side driver) 30 agnd analog ground 31 test_io2 rf front-end test input/output 2 32 atest_io1 rf front-end test input/output 1 gnd ground/backplane on exposed die pad
6 9207bs?rke?01/11 atmel ata5780 [preliminary] 2. system operation modes 2.1 operation mode overview this section provides an overview of the standard modes and the transition between them. in the off mode all the circuit blocks of the receiver are deactivated. the ic can be woken up by activating the pwron pin or npwron pins. in the idle modes most receiver circuits are deactivated. if not, at minimum the oscillators are deactivated. the atmel ? ata5780 features two idle modes. the first is idle_rc which only activates the rc oscillato r in the microcontroller section. the second one is idle_xto; in this mode the crystal oscillator is active in additional to the rc oscillators. in rx mode all the circuits necessary for receiving telegrams are active. in polling mode the receiver is switched between active mode and sleep mode to reduce cur- rent consumption. during active mode the receiver scans for a valid signal. if no valid signal is available, the receiver automatically goes into sleep mode. the polling cycle and the wake-up criteria can be set in the eeprom of the receiver. in the po lling scenario thre e different appli- cations can be covered: the remote keyless entry (rke), the tire pressure monitoring system (tpms), and the remote start (rs). for the rke up to three operating frequencies can be used. because of the flexibility of the ic the wake-up criteria and polling cycle for each application can be defined separately in the eeprom.
7 9207bs?rke?01/11 atmel ata5780 [preliminary] 3. description of system functions 3.1 off mode the purpose of this mode is to set the device in a condition with very low current consumption. for example a current consumption of 5na can be typically expected for a 3v application, which is a benefit for the battery application. all the circuits of the receiver, avcc, and dvcc are deactivated while in this mode so that the device will not be sensitive to any rf signals or spi commands. furthermore, all the ports are set as an input. to leave the mode, the receiver must be woken up using the pwron pin or npwron pins. 3.2 idle mode most parts of the circuit are deactivated in idle mode. it is advisable to set the avr ? core to power-down mode in order to achieve the lowest current consumption. the atmel ? ata5780 receiver provides 2 different idle modes, idle rc and idle xto. for id le rc the dvcc power supply is active and the avr core runs with eith er slow rc oscillator (src) or fast rc oscilla- tor (frc). dvcc, avcc, and xto are active in idle xto mode. 3.3 coding schemes an d modulation option the atmel receiver ata5780 works with manchester and nrz coding for system design flexi- bility. figure 3-1 shows the manchester coding polarity which is usually used in the application. because of its flexibility, system designers can configure the atmel receiver ata5780 using another polarity of the manchester coding. this can be set in the eeprom configuration. figure 3-1. manchester coding polarity 3.4 receiving (rx) mode the receiver?s rx mode can be started in two ways, first by using the ?start_rx_eeprom? spi command. in this case the command leads the loading of all channel parameters from the eeprom and starts rx mode. secondly, the rx mode starts after powe r on automatically as preselected in the eeprom. in this condition the ic automatically leaves off mode, checks the receiver configuration in the eeprom (tc2), loads all channel parameters from the eeprom and starts rx mode. 3.4.1 rx transparent mode and buffered mode if the transmitter or receiver buffer mode is set, the received telegram is stored in the 32-byte rx buffer first before it can be read via spi command. the atmel ata5780?s demodulator contains two different paths whose parameters can be set separately, e.g. the modulation type and data rate. both paths generally work simult aneously until the device receives initial valid data from one of the both paths. only this initia l valid data is stored in the rx buffer. because the buffer is a ring buffer, a special interrup t is defined for the microcontroller (e.g., the avr block) so that the stored data can be read out quickly. ? 1 ? ? 0 ?
8 9207bs?rke?01/11 atmel ata5780 [preliminary] in transparent mode, after the receiver recognizes the valid wake-up criterion the received data stream and a corresponding data clock are generated on tmdo and tmdo_clk directly. the wake-up cr iteria must be set in the eeprom. the first cr iterion is detection of bitcheck and the start bit. this is the criterion for a standard telegram format. the second one is the wake-up pattern and the sfid, which are part of a flexible telegram format. if the two demodulator reception paths (path a and path b) are activated, the signals generated on pin tmdo and tmdo_clk come from the path which has recognized the first successfully wake-up criterion. for analysis and monitoring purposes the ic offers another type of transparent signal. the pin trpa and trpb can be used for this purpose. the raw data received is generated at the selected pin. 3.4.2 modulation in receiving mode atmel ? ata5780 supports the typica l modulation types in short- range device applications, as well as ask and fsk modulation type s. the novel feature of this atmel receiver is its ability to receive gfsk modulated telegrams. 3.4.3 data rate using the buffer mode the receiver supports the data rate from 0.5kbps to 20kbps in man- chester coding, whereas in nrz coding the supported data rate range is between 1kbps and 40kbps. one of the important parameters for system sensitivity is the data rate tolerances. atmel ata5780 supports the receiving of signal with a data rate tolerance of up to 10% without any sensitivity loss. the guaranteed sensitivity loss is just 1db for data rate tolerance of up to 20%. 3.4.4 rx error handling this section describes the behavior of the device if a bit error or an id scan error occurs during the reception process. the discussed condition in this section is the receiving mode's state after the successful detection of an sfid or start bit. the rx error handlings can be set to receiver configuration 6 (tc6) in the eeprom. 3.4.5 controlling an external lna depending on the system requirement, higher reception path sensitivity may be required. an external low noise amplifier should be used to boost sensitivity. this device offers an rxac- tive output pin which can be used to bias the external lna. basically, the pin shows the active time of the receiver path and can supply a maximum of 4ma current consumption. the polarity of the rx_active pin can be set in the eeprom (irq/eve nt configuration). 3.4.6 protocol and telegram handling 3.4.6.1 simple telegram (fts = 0) a simple telegram consists of a preamble, start bit and data stream. the start bit is the part of the first data byte which must be different from the preamble sequence. if the preamble sequence is ?0000?? the start bit must be ?1?. conversely, the start bit must be ?0? if the pre- amble sequence is ?1111??.
9 9207bs?rke?01/11 atmel ata5780 [preliminary] figure 3-2. principle of the simple telegram whether a telegram is valid or not is decided using the bit check function and start bit as the synchronization point. this telegr am has less sustainability against noise. in order to guaran- tee that the receiver will not be woken up very often by environmenta l noise the bit number to be checked must be set to higher than 6. 3.4.6.2 flexible telegram support enabled (fts = 1) this kind of telegram offers mo re sustainability for th e communication link. this flexible tele- gram consists of a wake-up pattern (wup), a relatively short preamble and sfid preceding the data stream. between the wup and preamble a space can be inserted in which no carrier signal occurs. an optional stop bit may come at the end of the telegram. this is not absolutely necessary because the end of the telegram is recognized when a manchester code violation is detected. figure 3-3. principle of the flexible telegram 3.4.7 id scanning one novel feature of the receiver is id scanni ng used in combination with rx buffer mode. the receiver compares the rece ived id with the stored ids in the eeprom memory. up to 18 ids can be stored and each id can be 4 bytes long at the most. the number of the ids to be activated can be set in the id_en control regist er. the id length and the position of the id in the data stream can be specified in the idx_ctrl control registers. figure 3-4 illustrates where the id could be positioned in a data stream. figure 3-4. possible id position in a data stream pre a m b le 0000 0000 0000 0 10 11 data s t a rt bit wup s p a ce pre a m b le s f i d data s top bit pre bu r s t ( 8 bit) pre bu r s t + s t a rt b it ( 8 bit) 1. d a t a byte 2. d a t a byte 3 . d a t a byte 4. d a t a byte 5. d a t a byte 6. d a t a byte 7. d a t a byte 8 . d a t a byte 9. d a t a byte s t a rt id s c a nning idx s 00 s t a rt id s c a nning 0 1 s t a rt id s c a nning 1 0 s t a rt id s c a nning 1 1 10. d a t a byte
10 9207bs?rke?01/11 atmel ata5780 [preliminary] note: if a telegram with a valid id is received the receiver automatically reverts to idle mode. 3.4.8 rssi measurement the receiver offers digital rssi values and meas ures the rssi value of the received signal at regular intervals. this feature works in rx mode only. the measurement intervals must be set in the rssi configur ation of the eeprom. the measurement interval can be configured to be between 0.25ms and 4.0ms. the mea- sured rssi values are stored in a 32-byte rssi buffer. the rssi sampling is started the moment the start bit or sfid is successfully recognized. in case the rx mode is restarted or when the id check fails during polling, the rssi buffer pointer is set to the in itial values. depending on a defined buffer fill level th e device can gener- ate an event or interrupt which can be used to trigger the microcontroller. the following receiver states allow the rssi request to be activated: ? demodulator_stable ? bit/wup check or ?rx_mode the rssi can be used in both rx buffer and rx transparent mode. as a part of the flexible telegram support (fts = 1) the atmel ? ata5780 receiver allows the minimum and maximum rssi value to be defined as additional wake-up criteria. the minimum and maximum values are stored in sram with the initial values of 0x00 (min) and 0xff (maximum). with this initialization there is no restricted area and all telegrams with a valid wup check are accepted. 3.5 polling mode 3.5.1 overview the use of polling mode in the atmel ata5780 reduces current consumption. in this mode the receiver path alternates between active and sleep mode. during the short active mode the device scans for the valid telegram. during a relative short active period the wake-up (wup) logic verifies the incoming signal by checking th e telegram for a valid wake-up pattern or bit check. the device is able to detect two differ ent telegram types. the first one is the standard telegram type for which the wake-up criteria are the bit check and start bit. the second tele- gram type is a flexible telegram which is validated using a wake-up criteria pattern, sfid, etc. if no valid telegram is detected, the receiver returns to sleep mode. the device stays in active mode if a valid telegram is detected. the autonomous polling scenario of the atmel ata5780 allows three different application types to be combined: remote keyless entr y (rke), tire pressure monitoring system (tpms), and remote start (rs). the receiver path automatically scans for the valid telegrams of the three applications. for the rke a multi-channel system of up to three operating frequen- cies can be used. all polling scenario settings can be selected when configuring the eeprom. the frequency ranges, modulation, data rate, and the wake-up criteria of the three different application channels can be completely different. even the polling cycle of the rke, tpms, and rs system can uniquely be defined in the eeprom. this flexibility allows the combina- tion of three different application systems us ing a single device, which helps reduce system costs.
11 9207bs?rke?01/11 atmel ata5780 [preliminary] 3.5.2 polling cycle time the polling cycle time determines the average cu rrent consumption in rx polling mode. this is the time period between activation of two receiver paths. the cycle time can be pro- grammed to be between 0ms and 4000ms and is determined when setting timer 1. if reception path activation d epends on the eeprom configur ation, the polli ng mode is also started. this begins with a bit check or scanning for a valid wup. one enhanced feature of the device is the rf carrier detection during this phase in fsk applications. this shortens the active time when no signal can be detected. if a bit check/wup scan fails, the receiver goes into sleep mode or skips into the nex t defined frequency channel and application channel respectively. 3.5.3 rke channel statistic during polling mode this feature is only active in combination if a flexible telegram type is not supported (fts = 0). the receiver is able to use as many as three channels for rke/peg applications, thus enhancing sensitivity and making the receiver resistant to disturbance. the rke channel with the best reception characteristic is constant ly detected in rx polling mode and fast polling mode. this is done by measuring and comparing the rssi value for each rke channel during bit check/wup check. the channel with the lowest rssi signal is stored as the ?best channel? in the status register flag3 (bcrke 3:1). before transmission commences, the connected microcontroller can read out the best channel information and is able to begin transmission on this channel. note: the tpm and rs channel are not considered in the channel statistic! follow these steps to identify the be st rke channel during polling mode: during each polling cycle, the rke channel with the best recept ion behavior is determined and stored in a status register (flag 3, bcrke2:0). this is done by reading the rssi value dur- ing bit check/wup for each channel. the channel with the lowest rssi value (= undisturbed) is the channel with the best reception characteristic. when using multiple rke channe ls, transmitting shoul d always start with the channel which had the best reception characteristic in the pas t. this can be determined by reading the best channel status information (flag3) and starting transmission on the corresponding channel. this minimizes the response time for passive entry go applications.
12 9207bs?rke?01/11 atmel ata5780 [preliminary] 4. block description 4.1 general circuit descrip tion (system block (module)) figure 4-1 shows the simple system block diagram of ata5780. the crystal oscillator and the fractional-n p ll generate the reference signal for the mixer which down-converts the incoming signal to the if frequency of approx. 251khz. the atmel ? ata5780 covers the worldwide ism frequency ranges of 315mhz, 434mhz, 868mhz, and 915mhz. two completely different low noise amplifiers (lna) were designed for the low- and high-frequency band. the if signals are sa mpled using high resolution adc. the baseband signal processing is performed using the digital si gnal after the adc. the digital rssi signal is measured after the channel filter. two completely different reception paths a and b can be set, making the combination of settings more flexible. figure 4-1. simple system block diagram lna, mixer im a ge rej. rx d s p rfin_lb rfin_hb s pdt_rx s pdt_ant temp ( ? ) xto xtal1 xtal2 pb (0 to 7) data bu s pc (0 to 5) irq crc avcc dvcc v s rom avr cpu eeprom s ram w a tchdog timer s rc, frc o s cill a tor s clock m a n. de bu g wire nvm controller port b ( 8 ) s pi port c (6) ss i mod u l a tor front-end control 16 bit timer s 2x 8 bit timer s 3 x su pplie s a nd re s et fr a ction a l n-pll volt a ge monitor s pdt d a mping a d
13 9207bs?rke?01/11 atmel ata5780 [preliminary] 4.2 fractional-n pll and vco 4.2.1 vco calibration the vco calibration must be enabled in the eeprom (register calconf1 bit vcocale = 1). the maximum time for the calibration routine is approx. 150s. the operating frequency of the vco is approx. 1.5ghz to 2.0ghz the front-end register fevct contains the 4bit digital control word for the vco. 4.3 receive path 4.3.1 overview two lnas, for high band and low band respectively, are provided for optimal matching for each frequency range. an rf detector is included after the lna successfully detects overload of the receiver by a blocker. an overload event of this kind can be read out from the fe_spi address space. a switch with 0db/15db damping is included to allo w reception in the presence of strong block- ers. the damping is switched on and off by a control register bit located in the fe_spi address. this detector is activated during the pll start and the result is used to control the damping switches located in front of the lna to reduce the lna overload (the lna is the first over- loaded component in the reception path, damping after lna therefore does not increase large-signal capability). damping 15db before the lna therefore causes a sensitivity loss of 15db but enables the receiver to receive data in the presence of modulated blockers 15db exceeding i1dbkp = ?35dbm. this means, for example, that at 165khz if bandwidth and a modulated blocker with a peak value of ?17dbm at a distance of 5mhz, reception of a signal with 20kbit/s 20khz dev is possible with a sensitivity of ?91dbm. the resistors and capacitors in the process te chnology used have a tolerance of about 20%. digital correction is performed on-chip to ensure accurate resistors and capacitors and enable their use as a reference resistor for the pa, as load capacitors for the xto, and as an accurate loop filter for the pll. the resistors are calibrated with an on-chip reference resistor and the result is stored in the factory-locked eprom (xrow). the capacitor is calibrated by the frequency deviation in the xto and the result is stored in the factory-locked eeprom, resulting in highly accurate inte- grated load capacitors for the xto and less accurate capacitors in the loop filter. in rx mode the receiver is sensitive to signals coming from one corresponding transmitter (rke1, 2, 3, tpm or rs channel). rx mode is started after power on if it is preselected in the eeprom or if it can be started with an spi command.
14 9207bs?rke?01/11 atmel ata5780 [preliminary] 4.3.2 rx digital signal processing the rx dsp block performs digital signal proce ssing, decoding, and checking of the rx sam- ples from the adc. it delivers the raw data at the trpa/b pins, the decoded data at the tmdo output and finally the buffered data words from the rx buffer. 4.3.2.1 demodulator figure 4-2. simplified demodulator and clock recovery block for one path note: x represents path a and b dedicated demodulators are available for reception path a and b. this allows unique settings for each data path. the only limiting factor for di fferences is the common channel filter fixing a common bandwidth fo r both data paths. ask/fsk modulati on, data rates, and deviation can be set independently. the demodulator supports the following modulation schemes: ? ask ? fsk with a deviation range of 0.5khz to 80khz ?gfsk fading up to 1db per bit is tolerated by the demodulator. data rates for nrz or symbol rates for other coding schemes: ? min: 0.5kbaud ? max: 40kbaud a matched filter is available for manchester coding; therefore the supported data rates are higher than calculated from the symbol rate. the manchester data rate range is: 0.25kbit to 80kbits. the demodulator provides dpll-based data clock recovery for optimized sampling positions that tolerates single-bit errors. a s k demod. clock recovery s ign a l from ch a nnel filter f s k demod. amplit u de check d a t a filter dmcrx, dmpgx dmcdx dmcrx, s a s kx dmmx, dmatx dmmx, dmhax rxfox dmdrx s ym b ol clock trpx 1 0 manx ampx carx
15 9207bs?rke?01/11 atmel ata5780 [preliminary] the internal states of the demodulator are reset by disabling the complete rx dsp(rdcr.rden=0), by activating the power reduction for the channel filter (rdpr.prflt=1), or by activating only the power reduction for the reception path a/b (rdpr.prpta/b=1). in the demodulator block the signal is processed in two identical paths a and b operated in parallel. each single path consists of the following: ? demodulating part ? post-detection filtering ? data slicer ? clock recovery ? symbol check fsk demodulation the demodulator is based on a digital pll. the demodulating process starts with carrier fre- quency detection of the useful signal, which is the (assumed) dominant frequency within the spectrum in the channel filter. the demodulator is centered using the measured frequency off- set approaching the desired frequency. the time constant of the regulation loop is changed stepwise for this purpose. the final setting depends on the deviation and data rate of the sig- nal to be received and is stored separately for path a and b (in the value dmcrx.dmpgx). the effective bandwidth for the demodulation process is therefore smaller, resulting in a higher cnr. the duration of the carrier frequency detection and centering depends on the selected loop gain in dmcrx.dmpgx. the loop gain must be set to achieve an appropriate output signal for the expected deviation and data rate. please note that for a certain setting the supported frequency deviation range and data rate is limited. this block provides the frequency offset value rxfox of the received signal. the loop coefficients of path a and path b is changed during the first stage of reception in order to lock to the signal. the final value of a depends on dmpgx and b is 1/2048. ask demodulation the ask demodulation is achieved by calculat ing the magnitude of the complex (i-q) base- band signal in a logarithmic scale. before the sign al enters the filters it is limited to achieve the amplitude range from detected peak level down to 23db. the parameters of the peak detec- tion are scaled by the selected data rate range in each path. post-detection filtering (data filter) further filtering and decimation is done for signal paths a and b by a 2-stage filter followed by a data slicer. the first stage contains 2 nd order cic architecture with programmable down-sampling. the down-sampling ratio is 2 dmdrx.dmdnx . in addition, the signal is processed by a moving average filter whose length is derived from the dmdrx.dmax value.
16 9207bs?rke?01/11 atmel ata5780 [preliminary] this block has two outputs: ? manchester matched (manx) ? symbol-based (trpx also available to ext. pin) the symbol-based filter needs dc compensation which is performed by a feedback loop. this loop is invoked a certain time after an edge at the data slicer output has been detected. then the compensation value is held until the next edge. the control signal dmhx = 0 limits this hold sequence to the duration of three symbols. clock recovery a recovered clock based on detected edges is provided for sampling the filtered signal. the start sequence of a telegram is used to match to the data/symbol rate. the initial symbol rate is obtained from the dmdra/dmdrb register. rssi (digital) the rssi is calculated from the magnitude of the baseband signal and corrected by the gain of the channel filter. depending on the setting of dmdra/dmdna (data rate path a), a num- ber of 2dmdna raw samples are put together and an average value built. the peak value from these results is held and stored to the rssi register. the read process for the rssi value resets the max-hold circuit. symbol check this block checks the incoming signal qu ality needed to co ntrol the receiver. there are four checks which generate a pass or fail signal: 1. carrier check (fsk only) is derived from the fsk demodulator (similar to a lock detect) 2. modulation amplitude check (signal out of the post detection filter) 3. symbol timing check (compares the signal edge positions in relation to clock recovery) 4. manchester check (checks if the sampled symbols conform with manchester code) an ok signal is generated if there is no fail during a number of sym bols/bits, which can be programmed. 4.3.2.2 rx buffer two reception buffers are available. they are connected to the reception path a and b data outputs. this allows simultaneous reception of both modulation types or reception of the same modulation type with different data rate settings (tpm, rke). each buffer has its own interrupt for avr ? wake-up to allow data read-out before the next byte is received. if the data is not read out, it is overwritten by the following byte. a 32-byte receive buffer is available in the receiver and can be used for data reception. when starting rx mode the rx buffer pointer is set to the initial values (reset).
17 9207bs?rke?01/11 atmel ata5780 [preliminary] 4.3.3 transparent rx mode 4.3.3.1 tmdo / tmdo_clk the received data stream and a corresponding data clock are available on pin 17 (tmdo) and 19 (tmdo_clk) if the followin g conditions are fulfilled, ? rx transparent mode is enabled ? successful bitcheck/wake-up check ? valid startbit/sfid if the demodulator path a and path b are enabled, the first path to get a successful bit check or valid start bit/sfid is passed through to pin tmdo (pin17) and pin tmdo_clk (pin 19). 4.3.3.2 trpa / trpb this transparent signal is a raw signal directly from the demodulator output. 4.3.4 rssi an rssi buffer is provided to analyze the signal strength profile based on the telegram length. the rssi buffer length is 32 bytes. the rssi sample rate can be programmed to be between 250s and 4ms. the rssi buffer is organized as a ring-buffer and the customer must ensure there is buffer overflow. rssi sampling is started with the start bit/sfid okay. when starting rx mode or when the id check fails during polling, the rssi buffer pointer is set to the initial values (reset). 4.4 spdt block 4.4.1 receiver damping this feature allows a desired signal to be receiv ed in the presence of strong blockers. if the damping is activated, the reception path has 15db more attenuation. this damping can be set by a control register bit located in the front-end register. an rf detector is implemented in the lna circuitry which detects overload power in the lna stage. this condition can be read out via an spi command. this detector is activat ed during pll start and based on this result the damping switches are set. because the damping in this case is located in the front of the lna, overloading can be reduced. of course this overload protection of 15db l eads to a sensitivity loss of 15db, but it still enables data reception in the presence of modulated blockers 15db above the 1db compres- sion point (icp1db = ?35dbm).
18 9207bs?rke?01/11 atmel ata5780 [preliminary] 4.5 power management 4.5.1 introduction the ic has three power domains: ? vs - the unregulated battery voltage from the supply pin. ? dvcc - the regulated digital supply voltage. ? avcc - the regulated rf-front-end supply. each supply regulator has a corresponding rese t. the reset thresholds ensure correct opera- tion of the supplied circuits when the reset is de-asserted. this keeps inadvertent memory content loss from happening without notice. the avcc regulator has an additional threshold above the reset to ensure that the analog circuits are working properly. figure 4-3. power supply management overview 4.5.2 supplies the dvcc supply is enabled by a pin power- up. a pin power up happens when pwron is set to high or npwronx, are set to low for a time period longer than t power_on_req . the actual power-up source can be determined by reading the corresponding input ports. 4.5.2.1 avcc supply regulator the avcc supply regulator provi des the supply for the rf front end. it delivers a high output current while retaining close control of voltage. load transitions up to 3ma do not trigger the avcc low and reset indicators. this is necessary to allow timely activation of all front-end circuits. at supply voltages above 2.1v avcc load transi ents of more than 8ma are allowed without triggering the reset circuit. en_avcc rx/tx lv l s h d s p s rc, frc rf- front-end avr eeprom port b en_dvcc dvcc_ su p vmem_ su p avcc_ su p avcc 1. 8 to 1.9v dvcc 1. 3 to 1.4v v s 1.9 to 5.5v avcc_re s 1.7 to 1. 8 dvcc_re s 1.2 to 1. 3 l v l s h l v l s h p o r t c
19 9207bs?rke?01/11 atmel ata5780 [preliminary] 4.5.2.2 vs_pa supply regulator this regulator provides the supply voltage for the power amplifier in the rf front end. it has to be enabled every time a transmit operation is performed. 4.5.3 resets during reset, all i/o registers are set to their initial values and the program starts execution from the reset vector. the instruction placed at the reset vector mu st be a jmp - absolute jump - instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used and regular program code can be placed at these locations. this is also the case if the reset ve ctor is in the application section while the inter- rupt vectors are in the boot section or vice-versa. the circuit diagram in figure 4-4 on page 20 shows the reset logic. the i/o ports of the avr ? are immediately reset to their initial state when a reset source becomes active. this does not require a clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the hardware. 4.5.4 reset sources there are three sources for reset: ? brown-out (dvcc) reset. the mcu is reset when the supply voltage dvcc is below the brown-out reset threshold (vbot). the brown-out detector is always enabled. ? external reset. the m cu is reset when a low level is pr esent on the nreset pin at the external nreset input for longer than the minimum pulse length. ? watchdog reset. the mcu is reset when the watchdog is enabled and the watchdog timer period expires. the rf front end has a separate reset circuit for monitoring avcc voltage.
20 9207bs?rke?01/11 atmel ata5780 [preliminary] figure 4-4. reset logic 4.5.4.1 avcc voltage supervision the avcc voltage is enabled by the aven flag in the supcr. two thresholds are defined for avcc voltage monitoring: ? th_rst_avcc - indicates that the voltage is below the safe operating range of the digital circuits ? th_avcc_low - the voltage is below the safe operating voltage of the analog rf front end circuits both thresholds have a hysteresis and trigger a signal with a guaranteed minimum pulse to allow proper operation. 4.5.4.2 watchdog reset when the watchdog time s out, it will generate a short reset pu lse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . 4.5.4.3 external nreset an external reset is generated by a low level on the nreset pin. reset pulses falling below the minimum pulse width will generate a reset, even if the clock is not running. shorter pulses do not necessarily generate a reset. when the applied signal reaches the reset threshold volt- age - vrst - on its positive edge, the delay counter starts the mcu after the time-out period - t tout - has elapsed. dvcc_ok mcu s t a t us regi s ter (mcu s r) c a li b r a tion regi s ter s dvcc/vmem re s et dvcc/vmem su pply control regi s ter s re s et circ u it s pike filter w a tchdog timer internal re s et pwron nre s et npwron 1 npwron n v s & c a li b r a tion control cal_rdy r s t_dvcc port_w a ke s rc-o s cill a tor frc-o s cill a tor del a y co u nter s timeout counter re s et r q s porf wdrf extrf borf data b u s .... .... &
21 9207bs?rke?01/11 atmel ata5780 [preliminary] 6. package information 5. ordering information extended type number package remarks ATA5780-PNQW qfn32 5mm 5mm pb free title drawing no. rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 6.54 3 -5124.01-4 common dimen s ion s (unit of me asu re = mm) min nom note max s ymbol 2 expo s ed p a d 3 .6x 3 .6 packa g e: vqfn_5x5_ 3 2l 10/12/10 dimen s ion s in mm s pecific a tion s a ccording to din technic a l dr a wing s 0.02 0.05 0.0 a1 5 5.1 4.9 e 0.2 3 0. 3 0.16 b 0.5 b s c e 0.4 0.5 0. 3 l 3 .6 3 .75 3 .45 e2 3 .6 3 .75 3 .45 d2 5 5.1 4.9 d 0.2 0.25 0.15 a 3 0.9 1 0. 8 a top view d 3 2 1 8 pin 1 id e a 3 a a1 b l z 10:1 s ide view bottom view d2 e 3 2 25 9 17 24 16 8 1 e2 z
22 9207bs?rke?01/11 atmel ata5780 [preliminary] 7. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 9207bs-rke-01/11 ? section 5 ?ordering information? on page 21 changed
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